ASIC Physical Design, Staff Engineer

Job Description

Alternate Job Titles:

• ASIC Physical Design Engineer

We Are:

Join us to transform the future through continuous technological innovation.

You Are:

Experience in working on IO integration with Wire-bond or Flip-chip design would be a significant advantage.

What You'll Be Doing:

• Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows, including Design Initialization, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route, and chip finishing steps.
• Performing Physical Implementation of blocks starting from gate netlist till GDS out.
• Conducting signoff verifications, including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the implemented blocks.
• Writing MCMM and UPF for the block designs.
• Providing handoff data to other signoff closures like STA, Formality, Layout, and Reliability verification.
• Collaborating with cross-functional teams to ensure seamless project execution and delivery.

The Impact You Will Have:

• Ensuring the successful implementation and verification of digital blocks, contributing to the overall quality and performance of our ASIC designs.
• Enhancing the reliability and efficiency of our chip designs through meticulous verification processes.
• Driving innovation in chip design by implementing cutting-edge technologies and methodologies.
• Providing critical data and insights that support the successful signoff and integration of our chip designs.
• Contributing to the continuous improvement of our design flows and methodologies.
• Supporting the development of high-performance silicon chips that power a wide range of applications, from consumer electronics to advanced computing systems.

What You'll Need:

• In-depth understanding of the ASIC Physical design flow steps starting from Gate netlist.
• Experience in Testchip implementation and testing exposure.
• Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV).
• Exposure to FinFET designs.
• Experience in working on IO integration with Wire-bond or Flip-chip design.

Who You Are:

• Detail-oriented and thorough in your approach to design and verification.
• Strong problem-solving skills and the ability to think critically.
• Excellent communication and collaboration skills, with the ability to work effectively in cross-functional teams.
• Adaptable and open to learning new technologies and methodologies.
• A proactive mindset with a passion for continuous improvement and innovation.

The Team You'll Be A Part Of:

Together, we work on complex design challenges and drive innovation in the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.