Senior Staff RTL/Integration Design Engineer - Pune

Lattice Overview:

Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills:

Role specifics:

• This is a full-time individual contributor position located in Pune, India.
• The role will focus on FPGA projects concentrated in Pune and similar time zones.
• The qualified candidate will be an expert in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog.
• The qualified candidate will be expert in SoC integration and associated quality checks including lint, CDC, RDC , SDC etc.
• The role requires to work with architecture team to define micro architect and design spec.
• The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.

Accountabilities:

• Serve as a key contributor to FPGA design efforts.
• Drive logic design of key FPGA blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality.
• Ensuring design quality through assertions, checkers, and scripting.
• Develop strong relationships with worldwide teams.
• entor and develop strong partners and colleagues.
• Occasional travel as needed.

Qualifications:

• BS/MS/PhD Electronics Engineering , Electrical Engineering, Computer Science or equivalent.
• 14+ years of experience in driving logic design across a multitude of silicon projects.
• Expertise in SoC integration , defining micro-architecture and experience of selecting 3rd party IP.
• Experience in working with ARM processor, AXI, AMBA bus , safety and security protocols, debug architecture.
• Familiarity with FPGA designs, use-cases, and design considerations is a plus.
• Independent worker and leader with demonstrated problem-solving abilities.
• Proven ability to work with multiple groups across different sites and time zones.