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Livspace-Mumbai
Data Management Dashboard Maintenance
• manage large volume of data inflow from Alliance Partners and ensure timely updates of partners dashboards/ reports.
• Partner Sync Ups / Timely Cadence
• conduct timely catch ups with Alliance partners...
Cadence-Pune
About the Job :Cadence's IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing focus on the Automotive Safety market. We are seeking a Principal Design Engineer to join our Functional Safety...
Livspace-Mumbai
Data Management Dashboard Maintenance
• manage large volume of data inflow from Alliance Partners and ensure timely updates of partners dashboards/ reports.
• Partner Sync Ups / Timely Cadence
• conduct timely catch ups with Alliance partners...
Cadence-Bangalore
Job Summary : Join a growing and dynamic team and help lead the Design for Test activities for next generation of SoCs in advanced technology nodes. As part of the HSV SoC design team, you will be working to define and implement the Design-for-Test...
Livspace-Mumbai
Data Management Dashboard Maintenance
• manage large volume of data inflow from Alliance Partners and ensure timely updates of partners dashboards/ reports.
• Partner Sync Ups / Timely Cadence
• conduct timely catch ups with Alliance partners...
Cadence System Design and Analysis-Bangalore
Job Description
Be part of the Cadence Memory IP Group adn responsible for -
• Developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers
• Responsible for developing firmware in C and similar Embedded programming languages typically...
Livspace-Mumbai
Data Management Dashboard Maintenance
• manage large volume of data inflow from Alliance Partners and ensure timely updates of partners dashboards/ reports.
• Partner Sync Ups / Timely Cadence
• conduct timely catch ups with Alliance partners...
Cadence System Design and Analysis-Bangalore
Experience on industry standard ATPG tools like Cadence Modus.
• Experience with RTL lint tools like Jasper.
• Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.
• Programming in Perl/Tcl/Python...
Cadence System Design and Analysis-Bangalore
Job Description
Be part of the Cadence Memory IP Group adn responsible for -
• Developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers
• Responsible for developing firmware in C and similar Embedded programming languages typically...
Cadence System Design and Analysis-Bangalore
Position Description: Design Verification role for IP development team. B. Tech/M.Tech with 10+ years of relevant experience. Position is based in Bangalore/Noida, part of Cadence IP Group. Verification role for Serial and Interface Design IPs...
Cadence System Design and Analysis-Bangalore
nodes.
• Good hands on experience on scripting tcl & python.
Preferred qualifications:
• Experience in hardening DDR PHY designs.
• Experience in physical synthesis and constraints design.
• Experience in Cadence tools Innovus, Genus, Tempus & Voltus...
Cadence System Design and Analysis-Bangalore
like Cadence Modus.
• Experience with RTL lint tools like Jasper.
• Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.
• Programming in Perl/Tcl/Python or other scripting languages is a plus...
Ebizon-Noida
relationships with prospective clients across the world Lead qualification and nurturing Convert assigned leads into opportunities by running applicable cadence steps Collaborate with sales and marketing team members on strategic sales approach Develop...
mncjobsindia.com -
Cadence-Hyderabad
Experience level: 8-12 years
Education: BE/ B Tech/ ME/ M Tech / MS
• In-depth understanding of high-speed Serdes/Memory interface circuits like I/O's,PLL's, Clocking, Datapaths.
• Hands on experience on PCIe Gen3/4/5, GDDRx/DDRx/LPDDRx Serdes and...
Cadence-Hyderabad
Experience level: 8-12 years
Education: BE/ B Tech/ ME/ M Tech / MS
• In-depth understanding of high-speed Serdes/Memory interface circuits like I/O’s,PLL’s, Clocking, Datapaths.
• Hands on experience on PCIe Gen3/4/5, GDDRx/DDRx/LPDDRx Serdes and...
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